1. Field of the Invention
The invention relates to a semiconductor device, and more particularly to a trimming circuit and a method for internal voltage of a semiconductor memory device, such as a NAND-type flash memory, etc, and a semiconductor device comprising the trimming circuit.
2. Description of the Related Art
A flash memory includes an internal circuit that generates read-out voltages, write-in voltages and erases voltages. In the conventional method, for obtaining precise voltages, a voltage trimming circuit using a resistor ladder circuit and a comparator are generally used to control and adjust those internal voltages. However, when the voltage trimming circuit is used, in the strict sense, the internal voltages are lower or higher than target values because of the process variations of the comparator and resistors of the voltage trimming circuit. In this case, adjusting the trimming code to obtain precise voltages is needed.
As disclosed in Patent Document 1, FIG. 9 is a circuit diagram showing the configuration of a charge pump circuit 100 used in a flash memory according to the first prior art. The internal configuration and operation of the flash memory having the charge pump circuit 100 will be described later.
The flash memory shown in FIG. 9 comprises the charge pump circuit 100 for generating a boost voltage VP by boosting an external supply voltage VPP and a memory unit 101 driven by the boost voltage VP output from the charge pump circuit 100. Here, the charge pump circuit 100 comprises a pump circuit 110, a potential detecting circuit 111 and an oscillator circuit 112. The potential detecting circuit 111 detects whether the potential of the boost voltage VP reaches a predetermined potential so as to control the boosting operation of the pump circuit 110 to generate the predetermined boost voltage VP.
The pump circuit 110, a so-called Dickson charge pump, comprises a charge transferring means constituted by an NMOS transistor 142 having a drain where the external supply voltage VPP is applied, an NMOS transistor 143 having a drain connected to the source of the NMOS transistor 142, and an NMOS transistor 144 having a drain connected to the source of the NMOS transistor 143. In addition, the source of the NMOS transistor 144 is an output node of the pump circuit 110. Drains of the NMOS transistors 142˜144 are connected to their respective gates. A connecting node P1 connected between the NMOS transistor 142 and the NMOS transistor 143 is connected to one electrode of a capacitor C101. A connecting node P2 connected between the NMOS transistor 143 and the NMOS transistor 144 is connected to one electrode of a capacitor C102.
A clock signal CLK output from the oscillator circuit 112 and a detecting signal DET1 output from the potential detecting circuit 111 are input into the pump circuit 110. AND circuits 140 and 141 are controlled by the clock signal CLK and the detecting signal DET1. Furthermore, the clock signal CLK is input into the AND circuit 140 through an inverter G21 and is input into the AND circuit 141. Then, an output node N1 of the AND circuit 140 is connected to the other electrode of the capacitor C101, and an output node N2 of the AND circuit 141 is connected to the other electrode of the capacitor C102.
The potential detecting circuit 111 comprises resistors R1 and R0 connected in serial between the output node O1 of the pump circuit 110 and a common potential (such as ground potential) and a comparator CP1 having an inverse input terminal connected to a connecting node between resistors R1 and R0 and a non-inverse input terminal where a reference voltage VREF1 is input. The output of the comparator CP1 is taken as the detecting signal DET1 and is connected to the oscillator circuit 112 and the pump circuit 110.
The oscillator circuit 112 comprises an inverter G10 where the detecting signal DET1 is input, a clocked inverter G11 where the detecting signal DET1 is clock-input and the output of the inverter G10 is inversely clock-input, an inverter G12 where the output of the inverter G11 is input, and an inverter G13 where the output of the inverter G12 is input. The output of the inverter G13 is taken as the clock signal CLK and is connected to the pump circuit 110. In addition, the clock signal CLK is connected to the input of the inverter G11. Moreover, an NMOS transistor T1 is connected between a connecting node between the inverter G11 and the inverter G12 and the common potential. A gate of the NMOS transistor T1 is connected to the output of the inverter G10.
The charge pump circuit 110 used in the flash memory according to the first prior art as described above comprises a potential detecting circuit 111, including a resistor divider circuit DV1 constituted by the resistors R1 and R0 connected in serial, and a comparator CP1.
As disclosed in Patent Document 2, FIG. 10 is a circuit diagram showing the configuration of an internal voltage supplying circuit 200 according to the second prior art. As shown in FIG. 10, an external supply potential VCE is taken as an internal supply potential VCI through a PMOS transistor Q201 and is connected to a load 211. An inverse input terminal of a comparator 201 receives a reference potential Vref, and a non-inverse input terminal of the comparator 201 receives a divided internal supply potential DVCI which is taken as a feedback signal. A drain of the PMOS transistor Q201 is grounded through a resistor R211 and a resistor R212. Then, a voltage divided from the internal supply potential DVCI through the resistor R211 and the resistor R212 is taken as the divided internal supply potential DVCI and input into the non-inverse terminal of the comparator 201.
In the internal supply potential supplying circuit 200, according to the second prior art described above, an operating point of the comparator 201 may be freely selected regardless of set conditions of the internal supply potential VCI and the external supply potential VCE, and thus characteristics of the comparator 201 may be well maintained. Accordingly, the configuration may result in a special effect that the internal supply potential VCI is provided stably with a specific reference potential Vref.
As disclosed in Patent Document 3, FIG. 11 is circuit diagram showing the configuration of an internal voltage generating circuit 300 according to the third prior art. An example where the internal voltage generating circuit 300 comprises a DC-DC converter 313 is shown.
In FIG. 11, an internal supply voltage V0 from the DC-DC converter 313 is output to a logic circuit 306 and a voltage controlled oscillating unit 302 as well. The voltage controlled oscillating unit 302 outputs an oscillating signal having a frequency fv that corresponds to the input internal supply voltage V0 to a frequency comparing unit 311. For example, the frequency comparing unit 311 consists of a counter for counting the frequency of the output signal fv of the oscillating unit 302, a counter for counting a frequency of a reference clock fref, and a comparator for comparing the values of the two counters. The frequency comparing unit 311 may consist of a frequency/phase comparator for comparing frequencies and phases. Moreover, the frequency comparing unit 311 may also consist of a phase comparator. A controlling clock generating unit 312 controls the duty ratios of two clocks G1 and G2 according to the results of frequency comparison.
The internal voltage generating circuit 300 described above controls the internal supply voltage V0 according to the frequency fref of the reference clock.
FIG. 12 is a block diagram of a NAND-type flash memory 2E according to the fourth prior art.
In FIG. 12, the NAND-type flash memory 2E according to the fourth prior art comprises: a NAND-type flash memory block 10 including a data register 10R; a controller 20 controlling the operations of the whole NAND-type flash memory 2E; a reference voltage generator 30 that generates a predetermined reference voltage Vref; pump circuits 31-1˜31-N that boost the supply voltage to a predetermined voltage, which is a predetermined multiple of the reference voltage Vref; internal voltage generators 32-1˜32-N that generate predetermined internal voltages V1˜VN based on the reference voltage Vref and voltages from the pump circuits 31-1˜31-N; and a BIST (Built-in Self Test) circuit 3E connected to a test device 1 through a multi-purpose probing pad MP, wherein the test device 1 is an external device performing the testing of the memory chip. Here, the BIST circuit 3E comprises: a switch circuit 33 for outputting a selected one of the reference voltage Vref and the internal voltages V1˜VN as an internal voltage Vin according to a control signal from a trimming controller 35A; a resistor dividing circuit 36 for outputting a resistor-divided voltage divided from the internal voltage Vin by resistors; a comparator 37 for comparing the voltage from the resistor dividing circuit 36 and an external reference voltage EVref from a test device 1 and outputting a signal of the comparison results; and the trimming controller 35A for being operated based on the control signal from the controller 20, including a determining circuit for determining a signal from the comparator 37 so as to generate a control signal to the switch circuit 33, and performing voltage control on a reference voltage generator 30 and the internal voltage generators 32-1˜32-N.
FIG. 13 is a flow chart of an internal voltage trimming process performed by the trimming controller 35A shown in FIG. 12.
In FIG. 13, in step S1, the internal voltage Vin is set to a voltage that corresponds to the first trimming code (initial value). That is, the trimming code TC is set to be 1. Here, as the trimming code TC is changed, the voltage may change within a range of 6.0 V to 7.5 V by, for example, 0.5 V or 0.1 V at a time. Next, in step S2, switching to a programming mode of the memory is performed. In step S3, a waiting for the sake of circuit programming stability, such as a waiting with 20 μs, is performed. Then, in step S4, the internal voltage Vin is applied to the resistor dividing circuit 36. In step S5, a waiting with 10 ms considering a circuit time constant is performed. Moreover, in step S6, the comparator 37 and the trimming controller 35A are used to calculate an average value of ten internal voltages Vin which are measured at ten times. Then, in step S7, it is determined whether the average value of the internal voltage Vin is larger than a target value. If the result of step S7 is NO, the process proceeds to step S8. In step S8, by incrementing the trimming code TC by 1, the internal voltage Vin is incremented by a predetermined increment, and then the process proceeds to step S2 to repeat steps described above. If the average of the internal voltage Vin is larger than the target value in step S7, it is determined that the internal voltage Vin is close to and slightly exceeds the predetermined target value, and then the process ends.
Patent Documents
[Patent Document 1] JP 2009-232486
[Patent Document 2] JP H10-027026
[Patent Document 3] JP H09-285109
[Patent Document 4] JP 2001-229697